1. Field of the Invention
This invention generally relates to a semiconductor device, and, in particular, to a gate array type integrated circuit having a two dimensional array of basic cells.
2. Description of the Prior Art
A gate array device is well known in the art and it includes a two-dimensional array of logic cells which are selectively interconnected by metallization to define a desired logic function. Such a gate array device has a unique structure which is often referred to as the master-slice format. In accordance with this master-slice format, a plurality of basic cells are previously formed on a chip, and, then, according to the needs of a customer, an interconnection pattern for interconnecting selected ones of the basic cells to define a desired logic function is formed by metallization. Thus, such a master-slice format is suited for fabrication of a variety of integrated circuits in a short period of time at low cost.
However, in such a gate array device, when a function unit, such as a decoder for controlling memory cells, is constructed by using the basic cells of the gate array device, interconnections between the basic cells become extremely complicated and require a relatively large space. Thus, for example, as compared with the case in which use is made of a logic circuit device, such as a programmable logic array or simply PLA, the density tends to be lower. It is true that there has been proposed a master-slice type intergrated circuit having a plurality of alternately arranged logic and memory cell regions, whereby the memory cell regions may be selectively used as interconnection regions, as desired, as disclosed in the Japanese Patent Laid-open Pub. No. 59-11670. However, this Patent Laid-open Pub. only teaches to provide an intermediate memory cell/interconnection region between a pair of adjacent basic cell regions so that the intermediate region may be defined either as a memory cell region or as an interconnection region.